Abstract: Scaling of transistor features sizes has improves performance, increase transistor density and reduces the power consumption. As the threshold voltage is reduced due to scaling, it leads to increase in sub threshold leakage current and hence increase in static power dissipation. A chip’s maximum power consumption depends on its technology as well as its implementation. As technology scales down and CMOS circuits are powered by lower supply voltages, standby leakage current becomes significant. In our daily life, miniaturised and compact electronic devices are integral components. All devices need charging some amount of time. In discharging time, devices are in inactive state. Why electronic devices are become battery discharge? Because of leakage current. Transistor size becomes smaller and smaller and also it becomes faster and faster because of high density and threshold voltage falls i.e.., leakage of current. As considered scaling of VLSI geometries, consumption of static power is more influencing than others. In the VLSI, demanding of scaling and static power. Designers using stacked sleep transistor without penalization in power setup, delay and performance in circuit.

Keywords: VLSI (very large scale integration), CMOS (complementary metal oxide semiconductor),sleep transistor, cadence virtuoso.